Inducing the fault in any node and propagating the fault effect from the fault site to the primary output is called D-Algorithm.
D-Algorithm uses 5-valued logic (0, 1, D, D', X).
If,
D = 1, then No Fault
D' = 0, then No Fault
D = 0, then Fault
D' = 1, then Fault
Substrate
Substrate is known as supporting material. It provide mechanical support, electrical isolation, and thermal dissipation. Also it has high melting point (1400°C). So upon which or within which the elements of semiconductor device are fabricated or attached.
Live example: soil is the substrate for plants. Soil act as a supporting material for plant.
Intrinsic Semiconductor
Semiconductor that are pure, in other words free from impurities are called as Intrinsic Semiconductor. That is, number of existed electrons are equal to number of holes (e = p).
Extrinsic Semiconductor
If the impurities are doped to the pure semiconductor, then it becomes Extrinsic Semiconductor.
Doping
Doping is the process of adding impurities to the intrinsic semiconductors to change their properties. Normally Trivalent and Pentavalent elements are used to dope Silicon.
If the intrinsic semiconductor is dopped with trivalent (3 electrons) impurities, then it becomes p-type semiconductor.
Trivalent materials: Boron, Gallium, Aluminium (Acceptor Impurities)
If the intrinsic semiconductor is dopped with pentavalent (5 electrons) impurities, then it becomes n-type semiconductor.
Pentavalent materials: Phosphorus, Nitrogen, Arsenic (Donor Impurities)
Diffusion
Diffusion is the net movement of anything (electron, hole, atom, ions) generally from a region of higher concentration to region of lower concentration.
n-Well
n-Well is created in p-type substrate by digging well and putting n-type material in that well.
In p-type substrate, we can make nMOS.
In n-type substrate, we can make pMOS.
But in CMOS technology, we need both nMOS and pMOS transistors to build a circuit. Both nMOS and pMOS must be fabricated on the same silicon substrate (wafer).
The wafer are mostly p-type. So, we can only make nMOS transistors in those wafers. To fabricate a pMOS transistors, we dope a selected regions of the wafer to be n-type. By digging well and fill that well by n-type material is called as n-well.
N-channel MOSFET (NMOS): In an NMOS transistor, the semiconductor channel is made of n-type material (electron-rich). The gate voltage controls the flow of electrons from the source to the drain. When a positive voltage is applied to the gate with respect to the source, it creates an electric field that attracts electrons, forming a conductive channel between the source and drain, allowing current to flow.
P-channel MOSFET (PMOS): In a PMOS transistor, the semiconductor channel is made of p-type material (hole-rich). The gate voltage controls the flow of holes from the source to the drain. When a negative voltage is applied to the gate with respect to the source, it creates an electric field that attracts holes, forming a conductive channel between the source and drain, allowing current to flow.
"Setup Time" and "Hold Time" are important timing parameters in digital circuit design, particularly when dealing with flip-flops or registers.
Setup Time:
The setup time (Ts) is the minimum amount of time that the input signal must be stable before the active edge of the clock signal (rising or falling edge) arrives. In other words, the input data must be valid and unchanged for at least the setup time before the clock transition occurs. If the input changes too close to the clock edge, there might not be enough time for the flip-flop to properly capture the correct data.
Hold Time:
The hold time (Th) is the minimum amount of time that the input signal must remain stable after the active edge of the clock signal arrives. It ensures that the input data remains unchanged while the flip-flop captures the data. Changing the input too quickly after the clock edge can lead to data corruption or incorrect behavior.
Violations of setup and hold times can lead to timing-related issues, such as metastability, data corruption, or incorrect logic behavior. To ensure proper operation, digital designs must satisfy both setup and hold time requirements.
Designers typically analyze these timing parameters during the digital design process and perform static timing analysis to verify that these constraints are met. If the setup and hold times are not satisfied, appropriate measures must be taken, such as adjusting the clock frequency and optimizing logic paths.
Clock Skew:
The difference in the arrival time of a clock signal at two different registers, which can be caused by path length differences between two clock paths, or by using gated or rippled clocks.
Clock skew refers to the variation in arrival times of a clock signal at different points in a digital circuit. In other words, it is the difference in arrival times of the clock signal at various clocked elements, such as flip-flops, registers, and other sequential logic components. Clock skew can lead to
The time taken by the clock signal to reach from clock source to the clock pin of the particular flip flop is called as clock latency.
On-chip Clock Controller is a circuit or block to manage and control the clock signals of various on-chip components. The OCC is responsible for generating, distributing, and gating clock signals to ensure proper synchronization and timing of the chip's functional blocks.
OCC decides which clock to be probagated during Shift and Capture. Also decides how many clock pulses are required during Capture.
PLL is a circuit used to generate a stable and pricised clock signal from the noisy input signal. The PLL compare the input signal with reference signal and adjust the phase and frequency of the output signal.
A PLL is a feedback control system that compares the phase of an input reference signal with a feedback signal generated by a voltage-controlled oscillator (VCO). The PLL adjusts the VCO's frequency to match the reference frequency, generating a stable clock signal.
The main components of a typical PLL are:
The operation of a PLL is as follows:
Pin: An individual terminal or connection point on an electronic component.
Pad: A conductive area on a PCB or IC where a component's PIN is soldered for electrical connection.
Port: A group of related input or output pins in a digital system, often associated with a specific function or communication interface.
To add a half cycle delay between the two clock domain mixing in the data path or scan path to hold the data for half cycle to avoid hold violation.
Usually Negedge D-Latch is used as Lockup Latch.
Clock Divider is also called as Frequency Divider. Clock divider is a circuit, it takes a input (e.g. 100 MHz) and produce a output (e.g. 50 MHz) with lower frequency. It is used to generate different clock frequencies for different parts in the digital design.
Advantages:
1. Reduce the power consumption, in terms of slower clock.
2. Facilitate the testing and debugging, in terms of slowing down the clock.
Types:
Divided by 2 Clock Divider, Divided by 3 Clock Divider, Divided by 4 Clock Divider, and etc.
Clock gaters are used to reduce the power consumption, it is a technique/methodology to turn off the clock to certain parts of the digital design when not needed.
Simple AND gate may used as clock gater. But it has some limitation, that is it will create glitches.
Hence, the circuit with Negedge Latch and AND gate is used as clock gater.
CMOS - Complementary Metal Oxide Semiconductor
CMOS is a semiconductor technology used in most of the IC's. CMOS transistors are based on metal oxide semiconductor field effect transistor (MOSFET) technology.
CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistor (MOSFETs) to implement logic gates and other digital circuits.
MOSFET - Metal Oxide Semiconductor Field Effect Transistor.
MOSFET is a type of transistor used in electronic circuits for switching and amplification. It consist of metal gate electrode separated from the semiconductor channel by a thin layer of oxide, when voltage is appiled to the gate an electric field is created which controls the flow of current through the channel between the source and drain.
Source is connected to ground.
Drain is connected to load.
Gate is connected to input.
There are two main types of MOSFETs:
N-channel MOSFET (NMOS): In an NMOS transistor, the semiconductor channel is made of n-type material (electron-rich). The gate voltage controls the flow of electrons from the source to the drain. When a positive voltage is applied to the gate with respect to the source, it creates an electric field that attracts electrons, forming a conductive channel between the source and drain, allowing current to flow.
P-channel MOSFET (PMOS): In a PMOS transistor, the semiconductor channel is made of p-type material (hole-rich). The gate voltage controls the flow of holes from the source to the drain. When a negative voltage is applied to the gate with respect to the source, it creates an electric field that attracts holes, forming a conductive channel between the source and drain, allowing current to flow.
A transistor is a semiconductor device used to amplify or switch electrical signals and power. It is one of the basic building blocks of modern electronics.
It has three terminals, namely Collector, Base, Emitter.
The D flip-flop is a two-input flip-flop. The inputs are the data (D) input and a clock (CLK) input. The clock is a timing pulse generated by the equipment to control operations. The D flip-flop is used to store data at a predetermined time and hold it until it is needed.
The D flip-flop has two main inputs:
The D flip-flop has two outputs:
1. Schematic diagram
2. Logic diagram
A 2 × 1 multiplexer consists of two inputs IN1 and IN2, one select input SEL and one output OUT.
Logic diagram and Schematic symbol
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If SEL is 0, then IN1 will be selected.
If SEL is 1, then IN2 will be selected.
