On-chip Clock Controller is a circuit or block to manage and control the clock signals of various on-chip components. The OCC is responsible for generating, distributing, and gating clock signals to ensure proper synchronization and timing of the chip's functional blocks.
OCC decides which clock to be probagated during Shift and Capture. Also decides how many clock pulses are required during Capture.
In Test Mode,
If SE is 1 (Shift Phase), the Scan Clock is propagated at the output of OCC.
If SE is 0 (Capture Phase), the shift register starts shifting ‘1’ and enables the Clock Gate, to allow single pulse or double pulse, depending on the type of testing. The OCC generates one clock pulse in stuck-at testing (At-speed Mode = 0) and two clock pulses in at-speed testing (At-speed Mode = 1).
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