ATPG

ATPG - Automatic Test Pattern Generation

ATPG is to generate test patterns to detect the manufacturing faults in the design. 

Fault Models:

• Stuck-At
• Transition/Atspeed
• IDDQ
• Bridging
• Path Delay
• Cell Aware
• Small Delay Defect

ATPG Flow for Mentor Tool:

Setup Phase

• Reading Netlist, Libraries, Configuration files (dofile and testproc), provide declaration if any

Analysis Phase

• Check for DRC's
• Setup Fault Model - SA, TDF (LOS, LOC), IDDQ
• Setup fault list (add_faults -all)
• Generates patterns (create patterns for serial and parallel)

Fault Categories

• Fault Dominance
• Fault Equivalence
• Fault Collapse

Fault Dominance

A fault that can cover some of the faults with same input value are called as fault dominance.

Fault Equivalence

The faults which are covered automatically because of dominant fault with same input value are called as fault equivalence.

Fault Collapsing

Removing the equivalent faults from the total fault list is called as fault collapsing.

Coverage

It is a measure of percentage of faults that can be detected by the generated test patterns out of the total number of faults that exist in the design.

Example: 

If coverage is 99.5%, then the 99.5% of faults will get detected after manufacturing.

Fault Coverage = Total number of faults detectable / Total faults in the design

Test Coverage = Total number of faults detectable / Total testable faults

Coverage Benchmark:

Test Coverage for SA = 99.50%

Test Coverage for TDF = 85% to 90%

Coverage Between EDT and Bypass:

Coverage with EDT (compression) is slightly less when compared to coverage with Bypass.

Reason: Through the LFSR and Phase Shifter logic, the tool might not be able to generate some patterns which will detect some faults. But in uncompressed mode, it can generate those patterns.

with EDT -> 99.45%

with Bypass -> 99.50%

Coverage Between Stuck-At and Transition:

Coverage in Transition is less compared to Stuck-At.

Reason 1: Scenarios where one input of AND gate is tied to ground. Then the transition is blocked, no transition faults are detedcted. But we were able to detect 2 stuck-at faults.

Reason 2: Because of timing exceptions - (i) False Path, (ii) Multicycle Path.

Reason 3: In Stuck-at we will use only one clock domain (slow clock) for both Shift and Capture, whereas in Transition we will use two clock domains, i.e., slow clock for shift and fast clock for capture. So that there might be possible to get false path due to cross domain. 

AU.FP -> Faults untestable due to False Path.

AU.MCP -> Faults untestable due to Multicycle Path.

SDC file will contain False Path and Multicycle Path information.

SDC - Synopsys Design Constraints

False Path

A false path is a path that can not propagate a signal. That is the path that could not be activated by any combinations of inputs is called false path.

A false path does not required any timing analysis and must be excluded from timing analysis. 

Example 1:

    set_false_path -from {FF1} -to {FF4}

Example 2:

For asynchronous paths, designer will be declaring it as false path, so that the timing engine will not try to time the path.

CLK A and CLK B are asynchronous to each other (varying phase relationship throughout).

If Clk A and Clk B are asynchronous to each other, then we don't know exactly what is the time gap between Launch Edge and Capture Edge.

So the designer have to declare asynchronous path as false path.

DFT engineer also can not detect the TDF in these paths.

Multicycle Path

A multicycle path is an exception of default single cycle timing requirement path. That is on a multicycle path signal requires more than one clock cycle to propagate the data from source to destination.

Coverage Between LOC and LOS:

Fault Classes

Full Faults

• Testable Faults (TE)
• Detected (DT)
• Detected by Implication (DI)
• Detected by Simulation (DS)
• Undetected (UD)
• Uncontrolled (UC)
• Unobserved (UO)
• Possibly Detected
• PoSDet Testable (PT)
• PoSDet Untestable (PU)
• ATPG Untestable (AU)
• Block Boxes (BB)
• EDT Blocks (EDT)
• Pin Constraints (PC)
• Sequential Depth (SEQ)
• Tied Cell (TC)
• False Path (FP)
• Multicycle Path (MCP)
• On-chip Clock Controller (OCC)
• Hybrid LBIST (LBIST)
• IJTAG
• Low Pin Count Test (LPCT)
• Cell Constraints (CC)
• Hold PI (HPI)
• Mask Po (MPO)
• Undriven (UD)
• Wire (WIRE)

• Untestable Faults (UT)
• Tied Faults (TI)
• Blocked Faults (BL)
• Redudent Faults (RE)
• Unused Faults (UU)

Pattern Classification

DRC's:

D5 - Non-scan memory element 

• Reason: Flops in the LFSR logic, masking registors, pipeline flops are non-scan flops

E5 - X propagation violation 

• Reason: Initially LFSR logic is with X value, due to this X value only propagated at the time of Analysis