Design For Testability: Design For Testability

VLSI Flow/ASIC Flow

VLSI stands for Very Large Scale Integration, and it refers to the process of integrating a large number of transistors and electronic components onto a single semiconductor chip. The technology enables the creation of complex and high-performance integrated circuits (ICs) and microchips that power a wide range of electronic devices.

In the early days of semiconductor technology, individual transistors were manually assembled onto chips, leading to relatively simple circuits. With the advancements in manufacturing techniques, VLSI emerged as a significant breakthrough, allowing for the integration of thousands, millions, or even billions of transistors on a single chip.

Design Specification
↓
Design Code
↓
Code Verification
↓
Synthesis
↓
DFT
↓
Physical Design
↓
Timing Analysis
↓
Sign-off
↓
Tape-out

Design For Testability

Design for Testability (DFT) is a set of techniques used in the design of integrated circuits (ICs) to facilitate testing and validation during the manufacturing process. The primary objective of DFT is to ensure that the manufactured chips can be efficiently and effectively tested for defects or faults, thereby improving the overall quality and yield of the ICs.

DFT techniques (scan insertion, scan compression, mbist, ...) are integrated into the chip design to make it easier to detect and diagnose faults during testing.

In general, DFT is the technique used in IC’s to add testability features in order to detect the manufacturing defects at design process itself.

What is DFT? Why we need DFF?

DFT is a technique to detect the manufacturing defects in the design during design process itself by adding some extra logic to the design. That extra logic will provides testability features.

DFT will reduce test time and cost.

Advantages:

Reduced Test Time
Improved Test Coverage
Increased Yield and Cost-effectiveness

Disadvantage:

Area overhead

DFT Flow

Insertion
↓
Generation
↓
Validation

Insertion: Integrating extra features to the design.

Generation: Generating test patterns for different manufacturing defects.

Validation: Simulating the ATPG test patterns and validating it for correctness.

DFT Engineers vs. Verification Engineers

DFT Engineers:

DFT engineers focus on incorporating testability features and techniques into the chip's design to make it easier to test and validate during manufacturing. They work on integrating testability features such as scan chains, test access mechanisms (TAMs), built-in self-test (BIST) circuits, and other DFT structures into the design.

Verification Engineers:

Verification engineers focus on verifying and validating the functionality of the chip design against its intended specification.

Types of Manufacturing Defects:

Metal/Wire Scratches
Dark/Missing Vias
Poly Cracks
Metal/Poly Bridges

Types of Fault Models:

Fault models are used in the context of testing and verification of digital integrated circuits to simulate and analyze possible faults or defects that may occur during the manufacturing process. Various fault models exist to represent different types of faults in circuit components. Some common fault models include: