Simulation

Need of Simulation

• To validate the right database
• Validating right version of netlist, libraries etc., and solving all setup issues (like internal cut points used to clear off the DRC's temporarily) 
• To validate the test patterns generated by ATPG tool

Few Scenarios Why We Need Simulation:

1. To validate right files taken
2. To validate setup issues
3. To validate test patterns
4. Internal cut points can be used for temporary fix (to clear DRCs). But before the design given to tester, all these cut points should be removed. ATPG tool will generate a patterns by considering the internal cut points.  If the same pattern is given to the tester, our pattern will fail on the tester. So inorder to detect these kind of issues, we need to do simulation.
5. Suppose there is a false path (timing is not done) and if we have not told our tool that this is false path, tool will generate patterns along that false path. if it sent to tester, pattern will fail on tester. So we have to do simulation to find out. Inorder to overcome this kind of problems we go for timing simulation (delay of cells and nets will be considered)

Types of Simulation

• No-timing simulation
• Serial
• Parallel
• Timing simulation
• Serial
• Parallel

No-timing Simulation

• Only to check the logical operation and to check setup for correctness.
• Input Files: Netlist, Libraries, Testbench

Timing Simulation

• Logical check along with delay check (SDF file).
• Input Files: Netlist, Libraries, Testbench, SDF file
• SDF - Standard Delay Format, it consists of delay details, PVT (process, voltage, temperature), MIN delay, MAX delay.

Flow of Simulation

• Compilation: Tool will take library, netlist, and testbench and check for syntax errors.
• Elaboration: Elaborate the design and write the top module.
• Simulation: Apply the stimulus to DUT (Design Under Test)

Commands: vlog (compilation), vsim (elaboration, simulation)

Pattern Types

• Chain Test Pattern
• Scan Test Pattern

Chain Test Pattern

The tool will write set of patterns to perform chain test. That is to test the Q-SI path. Only shifting will happen in the simulation, there will not be any capture phase.

Scan Test Pattern

The tool will write set of patterns to check functional path. Both shifting and capturing will happen in the simulation.

• Serial Pattern
• Parallel Pattern

Serial Simulation

• Patterns are applied serially from PI, SI and the patterns are observed through PO, SO of the chip
• This is the way to apply patterns during post silicon validation

Disadvantages:

• Long simulation time
• Failure flop will not be reported directly in the log file

Parallel Simulation

• SI will be forced directly for each flop and Q output will be observed in next flop followed by capture pulse
• For each pattern only one clock pulse is required for shift as the patterns are loaded parallely, then the output is measured and compared with expected value
• Parallel simulation only used for debugging the failures (or) mismatch
• Scan chain failure can not be detected in parallel simulation

Advantages:

• Simulation time is less
• Easy to debug
• Failure flop will be reported directly in log file

Simulation Procedure

• Initially start with chain test, if it fail then try to figure out the chain path fail reason and correct it.
• After chain test pass, start no-timing simulation with serial pattern
• If it pass, then go for timing simulation.
• If it fail, then go for no-timing parallel simulation to find out the failure or mismatch reason to debug.
• In timing simulation, additionally input the SDF file along with netlist, library files, patterns/test bench file. Then start with serial simulation
• If it pass, then tape out.
• If it fail, then go for timing parallel simulation to find out the failure or mismatch reason to debug.

Note: Parallel simulation only for debug purpose. If serial simulation pass, then no need of parallel simulation.

Sample Makefile Command

rm -rf work

vlib work

vlog pattern_parallel.v -f verilog_files.list +nospecify -override_timescale 1ns/1ps -work work -l compile.log

vsim -c -debugDB -voptargs=+acc core_pattern_parallel_v_ctl -do "add wave -r /*; run -all" -c +nospecify -l simulation.log -wlf wave.wlf

+nospecify -> will disable all timing checks of cell/gates in library file

-override_timescale -> providing new timescale irrespetive to timescale mentioned in different verilog libs/netlists in verilog_files.list

-l -> writes/dumps a log file

-debugDB -> enables the design to view in Questasim schematic/visualizer

add wave -r /* -> will dump the waveform for all signals available in the design

-wlf -> waveform format to be dumped, so that can be viewed using QuestaSim

-voptargs -> to optimizing te design reading

+acc ->

-c ->

Simulation Debug

If there is mismatch in simulation then we get following message.

Error between simulated and expected patterns.

For debugging simulation mismatches, we use parallel simulation as we will exactly get which flop is failing.

Steps for Simulation Mismatch Debug:

In our simulation log, we have to check which flop is failing, at which pattern it is failing and at what time it is failing.

Create waveform dump by using below command for debugging.

vsim -c -debugDB -voptargs=+acc DmaWr_pattern_parallel_v_ctl -do "add wave -r /*; run -all" -c +nospecify -l simulation.log -wlf wave.wlf

We need to open QuestaSim waveform.

Command: vsim wave.wlf

We have to load the particular flop's waveform and go to the timestamp where the failure is happening. For the same flop, we have to open in our ATPG session and we have to load the failure pattern.

We have to trace till the point where there is a mismatch between ATPG and QuestaSim values.

1. To open waveform: 

    vsim wave.wlf

2. Then QuestaSim window will open

3. In which select the failing flop and right click and Add Wave, after that wave form window will open.

4. Select the zoom full option

5. Then arrange the input and output

6. Search the failing time stamp in waveform (search in nano second)

7. Run the ATPG session

8. Add the failing flop to visualizer

    add_display_instances <failing flop name>

9. After visualizer opened, add the failing pattern in Pattern Index.

10. Then trace back to find out where the issue caused

Sample Simulation Debug

• Whenever we get simulation mismatches, we need to debug using QuestSim and we should have an active ATPG session.
• We need to check in which flop, at what pattern, at what cycle, and at what time we are getting the mismatch from simulation log file.
• We need to open QuestSim waveform by giving vsim wave.wlf command.
• We have to load the particular flop's waveform. The same flop we have to open in ATPG visualizer.
• We have to trace till the point where there is a mismatch between ATPG and QuestaSim value.

Below is the mismatch details in the log file:

2600ns: Simulated response for chain chain 7: 1000110111 pattern 1 cycle 35

#2600ns: Expected response for chain chain 7: 0111010100 pattern 1 cycle 35

#2600ns: Mismatch at chain chain 7 cell 9 name Core_19_.Q, Simulated 1, Expected 0

It showing that flop Core_19 output pin is having mismatch (simulated 1, expected 0) at 1st pattern, 35th cycle, and at 2600 ns.

1. If we see the difference between QuestaSim and ATPG, we see that Q in Simulation is 1 but in ATPG is 0. The reason for the mismatch in Q is D. D in simulation is 1 but in ATPG is 0. So the culprit is D. Trace back the D pin in ATPG visualizer and add corresponding component in QuestaSim waveform.

2. If we see the difference between QuestaSim and ATPG, we see that Select line of the MUX in Simulation is 0 but in ATPG is 1. Because of the mismatch in select line, we are getting wrong output. So the culprit is select line. Trace back the select line in ATPG visualizer and load the corresponding component in QuestSim waveform.

3. If we see the difference between QuestaSim and ATPG, we see that the A input of AND gate in Simulation is 0 but in ATPG is 1. So the culprit is AND gate. Trace back the A input of AND gate in ATPG visualizer and load the corresponding component in QuestaSim waveform. 

4. If we see here, everything is same. Then the problem is in AND gate A input. So check the Netlist.

5. If we see here, in the netlist read during simulation, A input of AND gate is grounded by a mistake. So that we are getting this mismatch.

Netlist read during ATPG:

AND2X4 U6 (.A(net300567), .B(300468), .Y(338009));

Netlist read during Simulation:

AND2X4 U6 (.A(1'b0), .B(300468), .Y(338009));