Setup Time, Hold Time, Clock Skew, Clock Latency

"Setup Time" and "Hold Time" are important timing parameters in digital circuit design, particularly when dealing with flip-flops or registers.

Setup Time:

The setup time (Ts) is the minimum amount of time that the input signal must be stable before the active edge of the clock signal (rising or falling edge) arrives. In other words, the input data must be valid and unchanged for at least the setup time before the clock transition occurs. If the input changes too close to the clock edge, there might not be enough time for the flip-flop to properly capture the correct data.

Hold Time:

The hold time (Th) is the minimum amount of time that the input signal must remain stable after the active edge of the clock signal arrives. It ensures that the input data remains unchanged while the flip-flop captures the data. Changing the input too quickly after the clock edge can lead to data corruption or incorrect behavior.

Violations of setup and hold times can lead to timing-related issues, such as metastability, data corruption, or incorrect logic behavior. To ensure proper operation, digital designs must satisfy both setup and hold time requirements.

Designers typically analyze these timing parameters during the digital design process and perform static timing analysis to verify that these constraints are met. If the setup and hold times are not satisfied, appropriate measures must be taken, such as adjusting the clock frequency and optimizing logic paths.

Clock Skew:

The difference in the arrival time of a clock signal at two different registers, which can be caused by path length differences between two clock paths, or by using gated or rippled clocks.

Clock skew refers to the variation in arrival times of a clock signal at different points in a digital circuit. In other words, it is the difference in arrival times of the clock signal at various clocked elements, such as flip-flops, registers, and other sequential logic components. Clock skew can lead to 

• Violations of setup and hold time requirements.
• Reduced timing margins, which may affect performance.
• Potential for incorrect logic behavior.

Clock Latency:

The time taken by the clock signal to reach from clock source to the clock pin of the particular flip flop is called as clock latency.

Synchronous Clock vs. Asynchronous Clock

• Clock is generated by Oscillator.
• Clock is having two components :-
• Phase (used to describe the specific location)
• Frequency

Synchronous Clock:

Synchronous clock will have same phase and same source.

Asynchronous Clock:

Asynchronous clock will have different phase and different source.

OCC - On-chip Clock Control

On-chip Clock Controller is a circuit or block to manage and control the clock signals of various on-chip components. The OCC is responsible for generating, distributing, and gating clock signals to ensure proper synchronization and timing of the chip's functional blocks.

OCC decides which clock to be probagated during Shift and Capture. Also decides how many clock pulses are required during Capture.

In Test Mode,

If SE is 1 (Shift Phase), the Scan Clock is propagated at the output of OCC.

If SE is 0 (Capture Phase), the shift register starts shifting ‘1’ and enables the Clock Gate, to allow single pulse or double pulse, depending on the type of testing. The OCC generates one clock pulse in stuck-at testing (At-speed Mode = 0) and two clock pulses in at-speed testing (At-speed Mode = 1).

PLL - Phase Locked Loop

PLL is a circuit used to generate a stable and pricised clock signal from the noisy input signal. The PLL compare the input signal with reference signal and adjust the phase and frequency of the output signal.

A PLL is a feedback control system that compares the phase of an input reference signal with a feedback signal generated by a voltage-controlled oscillator (VCO). The PLL adjusts the VCO's frequency to match the reference frequency, generating a stable clock signal.

The main components of a typical PLL are:

• Phase Detector (PD): The phase detector compares the phase of the input reference signal (usually called the "reference signal" or "reference clock") with the phase of the feedback signal (usually called the "feedback signal" or "output clock"). It produces an error signal that represents the phase difference between the two signals.
• Voltage-Controlled Oscillator (VCO): The VCO is an oscillator whose output frequency can be controlled by applying a voltage. The VCO generates the output signal of the PLL, which is usually called the "output clock" or "PLL output." The frequency of the VCO is controlled by the error signal from the phase detector.
• Loop Filter: The loop filter is a low-pass filter used to filter the error signal from the phase detector and provide a smooth control voltage to the VCO. It helps stabilize the PLL and reduce jitter in the output signal.

The operation of a PLL is as follows:

1. The phase detector continuously compares the phase of the reference signal and the feedback signal and generates an error signal.
2. The error signal is filtered by the loop filter to obtain a smooth control voltage.
3. The control voltage is applied to the VCO, which adjusts its output frequency to minimize the phase difference between the reference signal and the feedback signal.
4. The output signal of the VCO becomes the feedback signal, which is fed back to the phase detector, completing the feedback loop.